(a) Field of the Invention
The present invention relates to a PDP (plasma display panel) driving method. More specifically, the present invention relates to a low voltage resetting PDP driving method.
(b) Description of the Related Art
Recently, flat displays such as LCDs (liquid crystal displays), FEDs (field emission displays), and PDPs have been widely developed. Among them, PDPs have higher luminance and wider viewing angles compared to other flat displays. Hence, PDPs have come into the spotlight as substitutes for conventional CRTs (cathode ray tubes) having screen sizes bigger than 40 inches.
The PDP is a flat display for using plasma generated via a gas discharge process to display characters or images. Tens of millions of pixels are provided thereon in a matrix format, depending on its size. PDPs are categorized into DC PDPs and AC PDPs, depending on driving voltages and discharge cell structures.
Since the DC PDPs have electrodes exposed in the discharge space, they allow the current to flow in the discharge space while the voltage is supplied, and therefore, they have a problem of requiring resistors for current restriction. On the other hand, the AC PDPs have electrodes covered by a dielectric layer. This structure naturally forms capacitance that restricts the current, and protects the electrodes from ion shocks in the case of discharging. Accordingly, they have a longer lifespan than the DC PDPs.
FIG. 1 shows a perspective view of an AC PDP.
As shown, a scan electrode 4 and a sustain electrode 5, disposed over a dielectric layer 2 and a protection film 3, are provided in parallel and form a pair with each other under a first glass substrate 1. A plurality of address electrodes 8 covered with an insulation layer 7 are installed on a second glass substrate 6. Barrier ribs 9 are formed in parallel with the address electrodes 8, on the insulation layer 7 between the address electrodes 8, and phosphor 10 is formed on the surface of the insulation layer 7 between the barrier ribs 9. The first glass substrate 1 and the second glass substrate 6 having a discharge space 11 between them are provided facing each other so that the scan electrode 4 and the sustain electrode 5 may respectively cross the address electrode 8. The address electrode 8 and a discharge space 11 formed at a crossing part of the scan electrode 4 and the sustain electrode 5 form a discharge cell 12.
FIG. 2 shows a PDP electrode arrangement diagram.
As shown, the PDP electrode has an m×n matrix configuration, and in detail, it has address electrodes A1 to Am in the column direction, and scan electrodes Y1 to Yn and sustain electrodes X1 to Xn in the row direction, alternately. Hereinafter, the scan electrode will be referred to as a Y electrode, and the sustain electrode as an X electrode. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG. 1.
FIG. 3 shows prior art PDP driving waveforms, and FIGS. 4A, 4B, 4C and 4D show wall charge distributions at each period when using a conventional driving method. That is, FIGS. 4A, 4B, 4C and 4D respectively show the charge distributions corresponding to parts (a), (b), (c) and (d) of the driving waveforms shown in FIG. 3.
As shown in FIG. 3, each subfield includes a reset period, an address period, and a sustain period according to the conventional PDP driving method.
In the reset period, the panel erases wall charges formed in the previous sustain discharge period, and sets a new wall charge state in order to make sure that the following address period performs appropriately.
In the address period, the panel selects the cells that will be turned on and accumulates wall charges of the cells to be turned on. In the sustain period, the panel keeps discharging at the addressed cells in order to display images.
A conventional operation during the reset period will be further described with reference to FIGS. 3 and 4A through 4D. As shown in FIG. 3, the conventional reset period includes an erase period, a Y ramp rising period, and a Y ramp falling period.
(1) Erase Period
When a final sustain discharge is finished, positive charges are accumulated to the X electrode, and negative charges to the Y electrode, as shown in FIG. 4A. The address voltage sustains 0 volts during the sustain period, but since it attempts to internally sustain an intermediate voltage of the sustain discharge, a great volume of positive charges are accumulated to the address electrode.
When the sustain discharge is finished, an erase ramp voltage that gradually rises from 0 (V) to +Ve (V) is supplied to the X electrode, and the wall charges formed to the X and Y electrodes are then gradually erased to enter the state shown in FIG. 4B.
(2) Y Ramp Rising Period
The address electrode and the X electrode are sustained at 0 volt during this period, and a ramp voltage that gradually rises from the voltage Vs to the voltage Vset is supplied to the Y electrode. Vs is lower than a firing voltage of the X electrode and Vset is higher than the firing voltage of the X electrode. While the ramp voltage is rising, a first weak reset discharge is generated to all discharge cells from the Y electrode to the address electrode and the X electrode. As shown in FIG. 4C, the results are accumulation of negative wall charges at the Y electrode, and positive wall charges at the address electrode and the X electrode concurrently.
(3) Y Ramp Falling Period
While the X electrode sustains a constant voltage Ve, a ramp voltage is supplied to the Y electrode. The ramp voltage gradually falls to 0 volt from the voltage Vs that is lower than the firing voltage of the X electrode. While the ramp voltage is falling, a second weak reset discharge is generated to all discharge cells. As a result, as shown in FIG. 4D, the negative wall charges at the Y electrode are reduced, and the polarity of the X electrode is inverted to store weak negative charges. Also, the positive wall charges at the address electrode are adjusted to be suitable for an address operation. If the panel is appropriately reset, the discharge cell sustains a voltage difference corresponding to the firing voltage Vf, as expressed in Equation 1.Vf,xy=Ve+Vw,xyVf,ay=Vw,ay  Equation 1
where Vf,xy represents the firing voltage between the X and Y electrodes; Vf,ay indicates the firing voltage between the address electrode and Y electrode; Vw,xy shows the voltage generated by the wall charges accumulated to the X and Y electrodes; Vw,ay denotes the voltage generated by the wall charges accumulated to the address electrode and the Y electrode, and Ve represents the externally supplied voltage between the X and Y electrodes.
As expressed in Equation 1, since the external voltage Ve (approximately 200 volts) is supplied between the X and Y electrodes, some wall charges sustain the firing voltage. However, no external voltage is supplied between the address electrode and the Y electrode. Therefore, the firing voltage is sustained only through the wall charges.
Referring to FIG. 4D, the charges marked with circles on the X and Y electrodes are not useful in sustaining the voltage difference between the X and Y electrodes. However, the charges are generated because many positive charges in the address electrode and negative charges in the Y electrode are stored respectively. This creates a voltage difference of as much as required for the firing voltage by using the wall charges between the address electrode and the Y electrode. According to the conventional method, a high voltage of Vset (about 380 volts) is required to perform sufficient discharging and to form the wall charges.
Therefore, in the conventional driving method, the voltage Vset higher than 380 volts has to be supplied so as to obtain a sufficient voltage margin, in order to reset the Y electrode. This requires components that can withstand higher voltage. Also, the conventional method generates high intensity of background light emission, rendering it difficult to achieve high contrast.